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Ambiguity/Inconsistency with schematics of logic gates from transistors


I am finding something confusing that doesn’t seem to make sense when making logic gates out of transistors. For example, making a NOT gate:


Why do we need two transistors? Why can’t we simply use the nMOS transistor? What is the purpose of the pMOS transistor in the diagram? If we remove it, we still have the same functionality as a NOT gate. When A is high, the voltage comes in from the top, and since electron current always follows the path of least resistance, it will go past Y to the ground, making Y output low. But if A is low, then the way is blocked, so it will travel through Y, giving Y as high output.

I am also seeing the same issues with pretty much all the other schematics that are given for the implementation of each logic gate with transistors. I have searched around and found several sources that show that you can make a NOT gate with just one transistor, a NAND with only 2 transistors, AND with only 2 transistors, and so on. Source 1, Source 2, Source 3. It seems that in the slides they all use twice the amount of transistors necessary and I don’t understand why.

Would very much appreciate an explanation (ideally before the midterm), thanks.


This is a CMOS circuit. It is a design method that uses NMOS and PMOS transistors ensuring that output is shorted to either ground or VCC but not both at the same time. The design also ensures that VCC is never shorted to ground.

Hope this helps